The invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of forming a storage electrode of a semiconductor memory device.
As the design rules of semiconductor memory devices continue to decrease, it becomes more difficult to form the memory devices in a limited area. For example, in the case of a DRAM, it has become more difficult to form a capacitor having sufficient capacitance in a limited area.
In a conventional semiconductor memory device, because photolithography and etching processes have been performed with a sufficient margin, a problem does not occur during the patterning process caused by a step difference or a surface roughness. However, as the design rules decrease, the process margin has also been reduced. As a result, the patterning problem caused by the step difference or the surface roughness is newly arising, and the number of process steps is significantly increased. Accordingly, reducing the number of processes and the manufacturing cost has become an important factor to determine the competitiveness of a device in the future.
Meanwhile, a storage electrode of a capacitor is electrically connected to a semiconductor substrate through a storage node contact. In order to form the storage node contact, an interlayer dielectric layer is formed in a state in which a word line and a bit line have been formed, and then a contact hole is formed to expose a predetermined area of the semiconductor substrate or a contact plug coupled to the semiconductor substrate. Subsequently, a conductive layer is deposited on an entire surface of the contact hole until the conductive layer has a predetermined thickness sufficient to fill the contact hole. At this time, the conductive layer generally includes a doped polysilicon layer. After that, the storage node contacts are separated from each other through a conventional etch back process using polysilicon etching gas, or a chemical mechanical polishing (CMP) process.
However, when performing the CMP process to separate the storage node contacts from each other after etching the polysilicon layer by using the polysilicon etching gas, a dishing phenomenon is observed and a severe wave-shaped topology is formed due to an over etch or an over CMP. Such a defective topology is transferred onto a mold insulating layer when depositing the mold insulating layer to form the storage electrode in the subsequent process, so that the mold insulating layer also has the defective topology. As a result, a pattern is improperly transferred and a pattern defect or a pattern deformation is incurred during the photo process for patterning the mold insulating layer.
After depositing the mold insulating layer, a planarization process of the mold insulating layer must be separately performed in order to prevent such a phenomenon; thus, this phenomenon causes a time loss and an economic loss. In addition, an over etch target must be set when performing the storage node etching process due to the defective topology, so the process margin may be significantly reduced in the photo and etching processes.